A 6.03 GHz Low Power Transimpedance Amplifier TIA in CMOS 0.18μm Technology

Abstract— A low power and high gain transimpedance amplifier (TIA) in 0.18μm CMOS technology is presented. TIA with better performance is realized by reducing the effects of input parasitic capacitor. A negative admittance output stage enables the transimpedance gain and the bandwidth to be improved. Cadence tools were conducted for this proposed TIA by utilizing RF transistor model based on 0.18μm HV CMOS process. Simulations are done with a single supply and the presence of a 50fF photodiode capacitance and 5fF loading capacitance. The core circuit occupies a chip area of 65μm×47μm. Simulation results show a -3dB bandwidth of 6.03GHz, a transimpedance gain of 54.3dBΩ and input referred noise current spectral density of 10.7pA/ HZ . The power dissipation is 2.33mW from 1.8V.